News, announcements, and analysis from the CHERI Alliance and its members. The complete archive is ordered with the newest article first.
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A new ETSI standard could rewrite the memory-safety debate
Memory-safety vulnerabilities remain one of the largest sources of critical software vulnerabilities. Despite years of investment in safer languages, hardware protections, and secure development practices, the industry has lacked a common way to define and compare memory-safety technologies.
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The leading Root-of-Trust now integrates CHERI security technology
If you are building secure hardware, the way you protect software running inside that hardware matters just as much as the cryptography around it.
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Combatting the AI threat with CHERI
In 2025 alone, global cybercrime costs reached an estimated $1.2 billion every minute, with projections rising to $1.8 billion per minute by 2029. Just seven years earlier, the figure was “only” $100 million per minute—already enormous, but now…
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Introducing the CHERI Adoption Global Ecosystem Assessment Q1 2026
In 2025 alone, global cybercrime costs reached an estimated $1.2 billion every minute, with projections rising to $1.8 billion per minute by 2029. Just seven years earlier, the figure was “only” $100 million per minute—already enormous, but now…
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One Bug is All It Takes
In 2025 alone, global cybercrime costs reached an estimated $1.2 billion every minute, with projections rising to $1.8 billion per minute by 2029. Just seven years earlier, the figure was “only” $100 million per minute—already enormous, but now…
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Why Codasip went all‑in on CHERI
Interview with Ron Black, CEO of Codasip
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CHERI memory safety mitigates LLM-discovered vulnerability in FreeBSD
Brooks Davis – Capabilities Limited
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Wind River Joins the CHERI Alliance
We are pleased to welcome Wind River to the CHERI Alliance, marking another important step forward in building a more secure computing ecosystem.
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AI has compressed the attack timeline
This article is part of a series of blogs published after the announcement of Mythos vulnerabilities’ exploitation capabilities. The views from other experts on this topic are:
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ICENI: First Look
For more than a decade, CHERI research has demonstrated that hardware enforced memory safety can eliminate entire classes of security vulnerabilities. Much of this work has taken place in simulators and FPGA platforms, enabling researchers and developers to experiment with capability based architectures before production hardware became available.
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The Capable Hub joins the CHERI Alliance to accelerate cybersecurity collaboration
We are excited to announce that The Capable Hub has become a member of the CHERI Alliance, a significant step forward in our mission to accelerate CHERI adoption. Improving the availability, quality, and upstream alignment of CHERI-enabled open-source software will make the design of CHERI-secured products easier and faster. This partnership underscores our collective commitment to fostering a collaborative ecosystem that enables companies to develop more secure products and drives innovation in cybersecurity.
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The EU Cyber Resilience Act: What It Means for Secure-by-Design Systems and CHERI
In 2025 alone, global cybercrime costs reached an estimated $1.2 billion every minute, with projections rising to $1.8 billion per minute by 2029. Just seven years earlier, the figure was “only” $100 million per minute—already enormous, but now eclipsed by today’s scale.
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Amid rising cyber threats, EnSilica joins the CHERI Alliance to enable safe & secure silicon
Oxford UK – 3 February 2026 – EnSilica, a leading provider of mixed-signal ASICs (Application-Specific Integrated Circuits), today announced that it has joined the CHERI Alliance. In a world facing an explosion of cyber threats, this collaboration will accelerate the adoption of a technology that could eliminate more than 70% of current vulnerabilities.
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Towards a reference QEMU for CHERI platform emulation
QEMU is one of the most popular open source machine emulators (https://www.qemu.org), with support for many CPU architectures, including x86_64, Arm and RISC-V.
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Secure and Resilient Systems in the Era of CRA and IoT
On 21 January 2026, technology leaders, engineers, security practitioners and compliance specialists will gather at IWM Duxford for Secure Horizons 2026, a one day, in person event hosted by EPS Global.
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Codasip Powers UK Digital Security by Design Innovation Contracts with CHERI Technology
Codasip
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CHERI or CHERIoT? The Answer Is Not What You Think
Interest in capability based security has grown rapidly as organisations look for practical ways to move beyond legacy memory protection. As more projects explore CHERI technologies, a common question keeps surfacing: should we use CHERI or CHERIoT? At first glance it sounds like a straightforward architectural decision, but as David Chisnall from SCI Semiconductor points out, the question itself rests on a false premise.
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Streamlining the CHERI Ecosystem: An Update from the Repository Management Working Group
Dr Marno van der Maas – CHERI Alliance
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New InnovateUK-funded project to merge CHERI support into FreeBSD
Brooks Davis – Capabilities Limited
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Innovate UK Project Winner: University of Birmingham
University of Birmingham
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You just missed the CHERITech’25 Conference – but wait, you can still attend the virtual replay!
The CHERITech’25 Conference was held on the 14th of November 2025 at the Sister – Renold Building, Manchester, bringing together leading figures from industry, academia and government to discuss the latest developments in Capability Hardware Enhanced RISC Instructions technology (CHERI) and Digital Security by Design (DSbD).
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Several CHERI Alliance members win the DSbD competition to deliver new CHERI chips and software
Exciting news for the CHERI community! The winners of the latest Digital Security by Design (DSbD) innovation competitions have been announced, and once again the CHERI Alliance is right at the heart of the action.
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lowRISC and Partners to Deliver Commercial-Quality, Open-Source CHERI Secure Enclave with InnovateUK Support
lowRISC CIC and Capabilities Limited, two founding members of the CHERI Alliance, have announced the launch of the COSMIC Project, supported by the UK Department for Science, Innovation and Technology (DSIT) and InnovateUK.
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CHERIoT 1.0 Specification Released
5 November 2025, Cambridge – New Release
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IoTSF + TechWorks – Resilient IoT and Trustworthy AI Conferences
30 October 2025, London – Event Recap
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CHERI Alliance to Distribute Arm Morello Boards – The Journey Beyond DSbD Continues!
The CHERI Alliance is now distributing Arm Morello boards – the CHERI development journey continues beyond DSbD.
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Behind the Scenes: inside the promotion and ambassador program Working Group
If you’ve been watching the CHERI Alliance gather momentum, you’ve probably noticed a growing wave of community activity—talks, demos, explainers, and friendly faces spreading the word about capability-based security. A lot of that energy is coordinated by the Promotion & Ambassador Program Working Group (WG). Here’s a clear look at what the WG does, how it empowers ambassadors, and how you can plug in.
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Siemens Joins the CHERI Alliance: a United Front for Cutting-Edge Cybersecurity
Cambridge, UK – 5 September 2025 – The CHERI Alliance announces that the Electronic Design Automation segment of Siemens Digital Industries Software has joined the non-profit organisation as a member to promote and enable a new level of cybersecurity in the EDA industry. This collaboration marks a significant milestone in CHERI’s mission to advance technological innovations and bolster security measures in the digital landscape.
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SCI Semiconductor and the CHERI Alliance at RISC-V Summit in China, July 2025
Andy Frame –
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CHERI-seL4 and CHERI-Microkit Released
Hesham Almatary
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Working Group Spotlight – Marketing
CHERI is reshaping how we think about secure technology. At the heart of this effort is the CHERI Alliance, a growing community committed to secure by design innovation. By joining us, you gain not just insight and influence but support in making your work more visible, more accessible and more impactful. The Alliance is organsied into Working Groups which are open to all members who want to participate.
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BT Group Joins the CHERI Alliance to Advance Cybersecurity Innovation
Cambridge, UK – 18 June 2025 – The CHERI Alliance, a global coalition dedicated to enhancing cybersecurity through groundbreaking hardware memory safety technology, is proud to announce that BT Group has joined its ranks. As one of the world’s leading telecommunications companies, BT brings decades of expertise in network security and innovation to the Alliance, further strengthening the mission to create a safer digital future.
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Unlocking the Future: A Roadmap for CHERI Technology Advancement
In the rapidly evolving landscape of cybersecurity, the quest for robust and secure hardware foundations has never been more critical. A groundbreaking paper from the Defence Science and Technology Laboratory (DSTL) – Biting the CHERI bullet: Blockers, Enablers and Security Implications of CHERI in Defence – sheds light on the transformative potential of CHERI (Capability Hardware Enhanced RISC Instructions) technology, offering a beacon of hope for enhancing cyber resilience. The paper described:
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Recent advances in CHERI enhancing stability, maturity, and accessibility as urged by the UK’s DSTL
Andy Lindsay & Carl Shaw – Codasip
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lowRISC and SCI Semiconductor Release Sunburst Chip Repository for Secure Microcontroller Development
“Open source release accelerates path to market for commercial CHERIoT-based secure microcontrollers, supporting industry adoption and innovation.”
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CHERIoT-Ibex Core is Open Sourced to Enable Memory Safe MCUs
Source: https://www.eetimes.com/cheriot-ibex-core-is-open-sourced-to-enable-memory-safe-mcus/
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Building a Safer Digital Future
The Call for Memory Safety Standards and CHERI’s Role
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‘Cybersecurity by Design – from Research to Industry’ — Conference Report
At the first CHERI Alliance conference, organised in partnership with CyNam and NCSC, we had a packed out event, with a full hall at Hub8 MX in Cheltenham for the opening keynote from Paul Waller (from the National Cyber Security Centre, NCSC, a part of GCHQ). His talk covered ways to incentivise the adoption of security in computing, covering government led initiatives both inside and outside of the UK with some thoughts on various market factors and the role of policy in influencing them.
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CHERI Alliance Officially Launches, Adds Major Partners including Google, to Tackle Cybersecurity Threats at the Hardware Level
CAMBRIDGE, the United Kingdom – November 12, 2024 – The CHERI Alliance CIC (Community Interest Company) today announced its official launch and the expansion of its membership, welcoming Chevin Technology (UK), Critical Technologies (USA), the Defence Science and Technology Laboratory (Dstl, UK), Google (USA), Light Momentum Technology Corporation (Taiwan), National Cyber Security Centre (NCSC, a part of GCHQ, UK), Parvat Infotech (India), SRI International (USA), TechWorks (UK), Trusted Computer Center of Excellence (USA), the University of Birmingham (UK), and the University of Glasgow (UK) as founding members.
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Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance
Open access to complete SDK with Linux kernel will simplify building and testing of CHERI-enabled RISC-V applications
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End-users demand memory safety in their systems
The Digital Security by Design all-hands conference was held last week in Leeds, and it was the opportunity to measure the progress of CHERI and see how much is already available.
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Initial members join CHERI Alliance to drive adoption of memory safety and scalable software compartmentalization
Founding members include Capabilities Limited, Codasip, the FreeBSD Foundation, lowRISC, SCI Semiconductor, and the University of Cambridge.
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UK Government report highlights the CHERI Alliance
The Department for Science Innovation and Technology (DSIT) of the British Government has published a report about CHERI adoption and diffusion, to “understand the potential market” for CHERI and “how the Department can encourage and support the adoption and diffusion of the technology in semiconductors”.
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The White House promotes CHERI as a solution for memory safety
The White House has published a report highlighting the need for “securing the building blocks of cyberspace”, where they highlight CHERI as a solution that can enable memory safety through hardware features, recognizing that re-writing existing code in memory-safe languages cannot be feasible.
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Beyond Software Patching
Jim Wallace – CHERI Alliance / Cre8Vantage
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CHERI Tag Bit Transport Overlay Standard version 0.9 released
Benjamin Fletcher – CHERI Alliance
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CHERI-Zephyr v0.4.0 Release
In this blog covering the fourth official development release of CHERI-Zephyr, we’ll look at what’s already CHERI-supported in the kernel and highlight some of the key features added over the course of development. Whether you’re interested in porting an existing Zephyr application, exploring new projects, evaluating CHERI-enabled software, or simply seeing how CHERI changes the behaviour of real systems, there’s plenty already included to begin experimenting.
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