News and analysis
The complete Alliance news archive, ordered with the newest article first.
48 results
News-
AI Doesn’t Need a Kill Switch. It Needs Boundaries
In the earlier articles in this series, we looked at why memory-safety vulnerabilities persist in critical infrastructure, and how CHERI can contain a compromised software component rather than allowing one failure to spread across the platform. AI takes that challenge a step further: how do we limit the authority of a component that is becoming part of the control loop?
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CHERI Tag Bit Transport Overlay Standard version 0.9 released
Over the last few months I’ve had the pleasure of working with members of the CHERI Alliance’s CHERI-in-SoC Working Group to put together the first version of the CHERI Tag Bit Transport Overlay Standard.
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Beyond Software Patching
Critical National Infrastructure (CNI) products may remain in service for 10, 15 or even 20 years. During that time, software changes, attack techniques evolve and regulation is now becoming more demanding.
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CHERI-Zephyr v0.4.0 Release
In this blog covering the fourth official development release of CHERI-Zephyr, we’ll look at what’s already CHERI-supported in the kernel and highlight some of the key features added over the course of development.
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A new ETSI standard could rewrite the memory-safety debate
Memory-safety vulnerabilities remain one of the largest sources of critical software vulnerabilities. Despite years of investment in safer languages, hardware protections, and secure development practices, the industry has lacked a common way to define and compare memory-safety technologies.
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The leading Root-of-Trust now integrates CHERI security technology
If you are building secure hardware, the way you protect software running inside that hardware matters just as much as the cryptography around it.
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Combatting the AI threat with CHERI
The UM Labs Unicus® platform protects applications ranging from voice and video calls, surveillance video, extended reality and IoT.
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Introducing the CHERI Adoption Global Ecosystem Assessment Q1 2026
The CHERI Alliance is pleased to publish the CHERI Adoption Global Ecosystem Assessment Q1 2026, a new report examining the current state of CHERI adoption across industry, research, government, and open communities.
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One Bug is All It Takes
This article is part of a series of blogs published after the announcement of Mythos vulnerabilities’ exploitation capabilities. The views from other experts on this topic are:
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Why Codasip went all‑in on CHERI
We thought it would be valuable to sit down with Ron Black, CEO of Codasip, to talk about the most recent news, discuss why the company has committed so strongly to CHERI, what market signals are driving that focus, and how Codasip sees the CHERI ecosystem—and the CHERI Alliance—evolving in the years ahead. Here is what he told us:
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CHERI memory safety mitigates LLM-discovered vulnerability in FreeBSD
This article is part of a series of blogs published after the announcement of Mythos vulnerabilities’ exploitation capabilities. The views from other experts on this topic are:
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Wind River Joins the CHERI Alliance
We are pleased to welcome Wind River to the CHERI Alliance, marking another important step forward in building a more secure computing ecosystem.
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AI has compressed the attack timeline
This article is part of a series of blogs published after the announcement of Mythos vulnerabilities’ exploitation capabilities. The views from other experts on this topic are:
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ICENI: First Look
For more than a decade, CHERI research has demonstrated that hardware-enforced memory safety can eliminate entire classes of security vulnerabilities. Much of this work has taken place in simulators and FPGA platforms, enabling researchers and developers to experiment with capability-based architectures before production hardware became available.
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The Capable Hub joins the CHERI Alliance to accelerate cybersecurity collaboration
We are excited to announce that The Capable Hub has become a member of the CHERI Alliance, a significant step forward in our mission to accelerate CHERI adoption.
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The EU Cyber Resilience Act: What It Means for Secure-by-Design Systems and CHERI
In 2025 alone, global cybercrime costs reached an estimated $1.2 billion every minute, with projections rising to $1.8 billion per minute by 2029. Just seven years earlier, the figure was “only” $100 million per minute—already enormous, but now eclipsed by today’s scale.
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Amid rising cyber threats, EnSilica joins the CHERI Alliance to enable safe & secure silicon
CHERI (Capability Hardware Enhanced RISC Instructions) is an open technology that fundamentally strengthens systems’ security by preventing memory corruption and unauthorized code execution—two of the most pervasive threats in modern computing.
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Towards a reference QEMU for CHERI platform emulation
QEMU is one of the most popular open source machine emulators (https://www.qemu.org), with support for many CPU architectures, including x86_64, Arm and RISC-V.
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Secure and Resilient Systems in the Era of CRA and IoT
On 21 January 2026, technology leaders, engineers, security practitioners and compliance specialists will gather at IWM Duxford for Secure Horizons 2026, a one day, in person event hosted by EPS Global.
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Codasip Powers UK Digital Security by Design Innovation Contracts with CHERI Technology
The UK government’s ambitious Digital Security by Design initiative continues to gain momentum, with Codasip playing a pivotal role in two key innovation contracts announced as part of the program’s £21 million investment to advance hardware-based cybersecurity technology.
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CHERI or CHERIoT? The Answer Is Not What You Think
Interest in capability based security has grown rapidly as organisations look for practical ways to move beyond legacy memory protection.
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Streamlining the CHERI Ecosystem: An Update from the Repository Management Working Group
The CHERI Alliance is dedicated to advancing the state-of-the-art in capability-based security. As our collaborative efforts and technical output grow, so does the need for a standardised, clear, and efficient way to manage that output. This is why the Repository Management Working Group was established: to systematically oversee all the technical collateral produced by the alliance.
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New InnovateUK-funded project to merge CHERI support into FreeBSD
CheriBSD has been a key part of the hardware-software design used to create CHERI since the project’s inception.
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Innovate UK Project Winner: University of Birmingham
At the University of Birmingham, in the Centre for Cyber Security and Privacy, we have over 15 years of combined experience working on the CHERI (Capability Hardware Enhanced RISC Instructions) architectures.
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You just missed the CHERITech’25 Conference – but wait, you can still attend the virtual replay!
The CHERITech’25 Conference was held on the 14th of November 2025 at the Sister – Renold Building, Manchester, bringing together leading figures from industry, academia and government to discuss the latest developments in Capability Hardware Enhanced RISC Instructions technology (CHERI) and Digital Security by Design (DSbD).
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Several CHERI Alliance members win the DSbD competition to deliver new CHERI chips and software
Exciting news for the CHERI community! The winners of the latest Digital Security by Design (DSbD) innovation competitions have been announced, and once again the CHERI Alliance is right at the heart of the action.
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lowRISC and Partners to Deliver Commercial-Quality, Open-Source CHERI Secure Enclave with InnovateUK Support
The 3 year initiative will deliver the first commercial-quality, open-source, CHERI-enabled 64-bit Secure Enclave for application-class system-on-chips (SoCs). By combining CHERI hardware memory safety and compartmentalisation with formal verification, COSMIC aims to create a secure foundation for future high-assurance silicon designs.
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CHERIoT 1.0 Specification Released
CHERIoT 1.0 provides a stable, hardware-enforced platform for building memory safe, compartmentalised systems in the microcontroller class. The specification defines the instruction set architecture, language extensions, and the complete compilation and relocation model, enabling developers to build software that is safeguarded against buffer overflows and use after free errors, even in hand written assembly.
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IoTSF + TechWorks – Resilient IoT and Trustworthy AI Conferences
The IoT Security Foundation (IoTSF) and TechWorks AI held their annual Resilient IoT and Trustworthy AI Conference on Thursday 30 October 2025 at the IET, Savoy Place, London. Delegates from industry, academia and government gathered to explore the evolving challenges of securing intelligent and connected systems.
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CHERI Alliance to Distribute Arm Morello Boards – The Journey Beyond DSbD Continues!
The CHERI Alliance is now distributing Arm Morello boards – the CHERI development journey continues beyond DSbD.
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Behind the Scenes: inside the promotion and ambassador program Working Group
If you’ve been watching the CHERI Alliance gather momentum, you’ve probably noticed a growing wave of community activity—talks, demos, explainers, and friendly faces spreading the word about capability-based security.
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Siemens Joins the CHERI Alliance: a United Front for Cutting-Edge Cybersecurity
Cambridge, UK – 5 September 2025 – The CHERI Alliance announces that the Electronic Design Automation segment of Siemens Digital Industries Software has joined the non-profit organisation as a member to promote and enable a new level of cybersecurity in the EDA industry.
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SCI Semiconductor and the CHERI Alliance at RISC-V Summit in China, July 2025
In the latter half of July I got the fantastic opportunity to re-visit Shanghai after a good few years of being away and wow, have I missed it. Shanghai is a fantastic city to visit and has grown so much over the last 20 years. It is therefore a fitting location and analogous to the growth of RISC-V celebrating its own 15th year anniversary.
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CHERI-seL4 and CHERI-Microkit Released
We are happy to release a prototype of CHERI-seL4, an experimental version of the seL4 microkernel with CHERI support. This comes with CHERI-Microkit, a lightweight userspace framework, and a set of exercises and tutorials designed to help developers explore CHERI’s potential in a real microkernel environment.
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Working Group Spotlight – Marketing
CHERI is reshaping how we think about secure technology. At the heart of this effort is the CHERI Alliance, a growing community committed to secure by design innovation. By joining us, you gain not just insight and influence but support in making your work more visible, more accessible and more impactful. The Alliance is organised into Working Groups which are open to all members who want to participate.
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BT Group Joins the CHERI Alliance to Advance Cybersecurity Innovation
The CHERI Alliance is an international consortium uniting industry leaders, researchers, and governments to drive the adoption of Capability Hardware Enhanced RISC Instructions (CHERI) technology. CHERI technology offers a transformative approach to preventing memory safety vulnerabilities, which are the root cause of certain cyberattacks, by incorporating hardware-enforced protections.
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Unlocking the Future: A Roadmap for CHERI Technology Advancement
In the rapidly evolving landscape of cybersecurity, the quest for robust and secure hardware foundations has never been more critical.
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Recent advances in CHERI enhancing stability, maturity, and accessibility as urged by the UK’s DSTL
The DSTL paper “Biting the CHERI bullet: Blockers, Enablers and Security Implications of CHERI in Defence” collates and analyzes feedback on CHERI development by 15 independent teams across industry and academia on the Morello research platform.
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CHERIoT-Ibex Core is Open Sourced to Enable Memory Safe MCUs
Source: https://www.eetimes.com/cheriot-ibex-core-is-open-sourced-to-enable-memory-safe-mcus/
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lowRISC and SCI Semiconductor Release Sunburst Chip Repository for Secure Microcontroller Development
Source: https://lowrisc.org/news/lowrisc-and-sci-semiconductor-release-sunburst-chip-repository-for-secure-microcontroller-development/
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Building a Safer Digital Future
The conversation around software memory safety is reaching a critical turning point. In a recent publication in the Communications of the ACM, industry experts have called for a decisive move toward standardizing principles and practices to mitigate memory safety vulnerabilities.
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‘Cybersecurity by Design – from Research to Industry’ — Conference Report
At the first CHERI Alliance conference, organised in partnership with CyNam and NCSC, we had a packed out event, with a full hall at Hub8 MX in Cheltenham for the opening keynote from Paul Waller (from the National Cyber Security Centre, NCSC, a part of GCHQ).
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CHERI Alliance Officially Launches, Adds Major Partners including Google, to Tackle Cybersecurity Threats at the Hardware Level
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Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance
“As more organizations and governments discover the potential of the CHERI technology to protect us, we need to speed up the pace of making the technology available in real systems,” says Ron Black, chief executive officer, Codasip.
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End-users demand memory safety in their systems
The Digital Security by Design all-hands conference was held last week in Leeds, and it was the opportunity to measure the progress of CHERI and see how much is already available.
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Initial members join CHERI Alliance to drive adoption of memory safety and scalable software compartmentalization
The initial founding members of the CHERI Alliance include Capabilities Limited, Codasip, the FreeBSD Foundation, lowRISC, SCI Semiconductor, and the University of Cambridge.
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UK Government report highlights the CHERI Alliance
The Department for Science, Innovation and Technology (DSIT) of the British Government has published a report about CHERI adoption and diffusion, to “understand the potential market” for CHERI and “how the Department can encourage and support the adoption and diffusion of the technology in semiconductors”.
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The White House promotes CHERI as a solution for memory safety
The White House has published a report highlighting the need for “securing the building blocks of cyberspace”, that highlights CHERI as a solution that can enable memory safety through hardware features, recognizing that re-writing existing code in memory-safe languages cannot be feasible.
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